1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to transistor architectures that enable an extended functionality of transistor devices, thereby providing the potential for simplifying the configuration of circuit elements, such as registers, static RAM cells, and the like.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices, and the like, a huge number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over the recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. However, the continuing scaling of feature sizes involves great efforts in redesigning process techniques and developing new process strategies and tools to comply with new design rules. Generally, in complex circuitry including complex logic portions, the MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption. In integrated circuits including logic portions formed by the MOS technology, a large number of field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which may influence, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
FIG. 1a schematically shows a cross-sectional view of a typical field effect transistor element as may be used in modern MOS-based logic circuitry. A transistor element 100 comprises a substrate 101, for instance a silicon substrate having formed thereon or therein a crystalline region 102 on and in which further components of the transistor element 100 are formed. The substrate 101 may also represent an insulating substrate having formed thereon a crystalline semiconductor layer of specified thickness that accommodates further components of the transistor 100. The crystalline region 102 comprises two or more different dopant materials in a varying concentration to obtain the desired transistor function. To this end, highly doped drain and source regions 104 defining a first conductivity type, for instance, an N-conductivity, are formed within the crystalline region 102 and have a specified lateral and vertical dopant profile. On the other hand, the crystalline region 102 between the drain and source regions 104 may be doped with a material providing the opposite conduc- trinity type, that is, as in the example shown, a P-conductivity, to produce a PN junction with each of the drain and source regions 104. Moreover, a relatively thin channel region 103 may be established between the drain and source regions 104 and it may be doped with a P-type material when the transistor 100 is to represent an N-channel enhancement transistor, or which may be slightly doped with an N-type material when the transistor 100 is to represent an N-channel depletion transistor. Formed above the channel region 103 is a gate electrode 105, which is separated and thus electrically insulated from the channel region 103 by a thin gate insulation layer 106. In a typical modem transistor element, sidewall spacers 107 may be provided at sidewalls at the gate electrode 105, which may be used during the formation of the drain and source regions 104 by ion implantation and/or in subsequent processes for enhancing the conductivity of the gate electrode 105, which is typically comprised of doped polysilicon in silicon-based transistor elements. For convenience, any further components such as metal silicates and the like are not shown in FIG. 1a. 
As previously mentioned, an appropriate manufacturing process involves a plurality of highly complex process techniques, which depend on the specified design rules that prescribe the critical dimensions of the transistor element 100 and respective process margins. For example, one essential dimension of the transistor 100 is the channel length, i.e., in FIG. 1a, the horizontal extension of the channel region 103, wherein the channel length is substantially determined by the dimension of the gate electrode 105 since the gate electrode 105, possibly in combination with any sidewall spacers, such as the spacers 107, is used as an implantation mask during the formation of the drain and source regions 104. As critical dimensions of advanced transistor elements are presently at approximately 50 nm and even less, any further progress in enhancing performance of integrated circuits entails great effort in adapting established process techniques and in developing new process techniques and process tools. Irrespective of the actual dimensions of the transistor element 100, the basic operations scheme is as follows. During operation, the drain and source regions 104 are connected to respective voltages, such as ground and supply voltage VDD, wherein it is now assumed that the channel region 103 is slightly P-doped to provide the functionality of an N-channel enhancement transistor. It is further assumed that the left region 104 is connected to ground and will thus be referred to as the source region, even though, in principle, the transistor architecture shown in FIG. 1a is symmetric with respect to the regions 104. Hence, the region 104 on the right-hand side, connected to VDD, will be referred to as the drain region. Moreover, the crystalline region 102 is also connected to a specified potential, which may be ground potential and any voltages referred to in the following are considered as voltages with respect to the ground potential supplied to the crystalline region 102 and the source region 104. Without a voltage supplied to the gate electrode 105 or with a negative voltage, the conductivity of the channel region 103 remains extremely low, since at least the PN junction from the channel region 103 to the drain region 104 is inversely biased and only a negligible number of minority charge carriers is present in the channel region 103. Upon increasing the voltage supplied to the gate electrode 105, the number of minority charge carriers, i.e., electrons, in the channel region 103 may be increased due the capacitive coupling of the gate potential to the channel region 103, but without significantly increasing the total conductivity of the channel region 103, as the PN junction is still not sufficiently forward-biased. Upon further increasing the gate voltage, the channel conductivity abruptly increases, as the number of minority charge carriers is increased to remove the space charge area in the PN junction, thereby forward-biasing the PN junction so that electrons may flow from the source region to the drain region. The gate voltage at which the abrupt conductivity change of the channel region 103 occurs is referred to as threshold voltage VT.
FIG. 1b qualitatively illustrates the behavior of the device 100 when representing an N-channel enhancement transistor. The gate voltage VG is plotted on the horizontal axis, while the vertical axis represents the current, that is the electrons, flowing from the source region to the drain region via the channel region 103. It should be appreciated that the drain current depends on the applied voltage VDD and the specifics of the transistor 100. At any rate, the drain current may represent the behavior of the channel conductivity, which may be controlled by gate voltage VG. In particular, a high impedance state and a high conductivity state are defined by the threshold voltage VT.
FIG. 1c schematically shows the behavior of the transistor element 100 when provided in the form of an N-channel depletion transistor, i.e., when the channel region 103 is slightly N-doped. In this case, the majority charge carriers (electrons) provide for conductivity of the channel region 103 for a zero gate voltage, and even for a negative gate voltage, unless the negative gate voltage is sufficiently high to create sufficient minority charge carriers to establish an inversely biased PN junction, thereby abruptly decreasing the channel conductivity. The threshold voltage VT is shifted to negative gate voltages in the N-channel depletion transistor when compared with the behavior of the N-channel enhance- ment transistor.
It should be noted that a similar behavior is obtained for P-channel enhancement and depletion transistors, wherein, however, the channel conductivity is high for negative gate voltages and abruptly decreases at the respective threshold voltages with a further increasing gate voltage.
On the basis of field effect transistors, such as the transistor element 100, more complex circuit components may be created. For instance, storage elements in the form of registers, static RAM (random access memory), and dynamic RAM represent an important component of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements significantly influence the overall performance of the CPU. Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells. Typically, a dynamic RAM cell comprises a storage capacitor and a single transistor, wherein, however, a complex memory management system is required to periodically refresh the charge stored in the storage capacitors, which may otherwise be lost due to unavoidable leakage currents. Although the bit density of DRAM devices may be extremely high, a charge has to be transferred from and to storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption when compared to static RAM cells. On the other hand, static RAM cells require a plurality of transistor elements to allow the storage of an information bit.
FIG. 1d schematically shows a sketch of a static RAM cell 150 in a configuration as may typically be used in modern integrated circuits. The cell 150 comprises a bit cell 110 including, for instance, two inversely coupled inverters 111. The bit cell 110 may be connectable to a bit line 112 and to an inverse bit line 113 (not shown in FIG. 1d) by respective select transistor elements 114, 115. The bit cell 110, that is, the inverters 111, as well as the select transistor elements 114, 115, may be formed of transistor elements, such as the transistor 100 shown in FIG. 1a. For example, the inverters 111 may each comprise a complementary pair of transistors 100, that is, one P-channel enhancement transistor and one N-channel enhancement transistor coupled as shown in FIG. 1d. Likewise, the select transistor elements 114, 115 may be comprised of N-channel enhancement transistors 100.
During operation of the RAM cell 150, the bit cell 110 may be “programmed” by pre-charging the bit lines 112, 113, for example with logic high and logic zero, respectively, and by activating the select line 116, thereby connecting the bit cell 110 with the bit lines 112, 113. After deactivating the select line 116, the state of the bit cell 110 is maintained as long as the supply voltage is connected to the cell 150 or as long as a new write cycle is performed. The state of the bit cell 110 may be retrieved by, for example, bringing the bit lines 112, 113 in a high impedance state and activating the select line 116.
As is evident from FIG. 1d, high operating speeds are achievable with the cell 150 due to the absence of storage capacitors, and a simplified management in reading and writing the bit cell 110 is provided since any synchronization with refresh pulses is not necessary. On the other hand, at least six individual transistor elements 100 are required for storing an information bit, thereby rendering the architecture of the cell 150 less space efficient. Hence, frequently a trade-off has to be made with respect to bit density in relation to speed and performance requirements.
In view of the problems identified above, a need exists for an improved device architecture that enables the formation of storage elements in a more space efficient manner.